1. Field of Invention
The invention relates to the field of forming interconnect layers in semiconductor integrated circuits, particularly in connection with damascene process.
2. Prior Art
Low k dielectrics are favored in the formation of interconnect layers in integrated circuits because they reduce the parasitic capacitance between the conductors in these layers. In some cases, the low k dielectric materials are difficult to etch, for instance, they etch slowly and costly equipment is required for their etching. This is the case for a carbon-doped oxide.
FIGS. 1A-1D show typical prior art processing which requires etching twice through the trench region of an interlayer dielectric (ILD). As shown in FIG. 1A, a first opening 10 is formed to define the vias. Now, another low k dielectric etching step is needed as shown in FIG. 1B, to define the trench 11 over the underlying via opening. Then as shown in FIG. 1C, the dielectric etchant stop used between the interconnect layers is removed to expose the underlying conductor. FIG. 1D illustrates the formation of a conductive barrier material to line the via and trench opening. As can be seen, the trench region of the ILD is etched through twice, once as shown in FIG. 1A and again, as shown in FIG. 1C. This is both time consuming and costly for some otherwise desirable low k dielectrics.